Enum kos_sys::dc::perfctr::perf_cntr_event_t

#[repr(C)]
pub enum perf_cntr_event_t {
    PMCR_INIT_NO_MODE = 0,
    PMCR_OPERAND_READ_ACCESS_MODE = 1,
    PMCR_OPERAND_WRITE_ACCESS_MODE = 2,
    PMCR_UTLB_MISS_MODE = 3,
    PMCR_OPERAND_CACHE_READ_MISS_MODE = 4,
    PMCR_OPERAND_CACHE_WRITE_MISS_MODE = 5,
    PMCR_INSTRUCTION_FETCH_MODE = 6,
    PMCR_INSTRUCTION_TLB_MISS_MODE = 7,
    PMCR_INSTRUCTION_CACHE_MISS_MODE = 8,
    PMCR_ALL_OPERAND_ACCESS_MODE = 9,
    PMCR_ALL_INSTRUCTION_FETCH_MODE = 10,
    PMCR_ON_CHIP_RAM_OPERAND_ACCESS_MODE = 11,
    PMCR_ON_CHIP_IO_ACCESS_MODE = 13,
    PMCR_OPERAND_ACCESS_MODE = 14,
    PMCR_OPERAND_CACHE_MISS_MODE = 15,
    PMCR_BRANCH_ISSUED_MODE = 16,
    PMCR_BRANCH_TAKEN_MODE = 17,
    PMCR_SUBROUTINE_ISSUED_MODE = 18,
    PMCR_INSTRUCTION_ISSUED_MODE = 19,
    PMCR_PARALLEL_INSTRUCTION_ISSUED_MODE = 20,
    PMCR_FPU_INSTRUCTION_ISSUED_MODE = 21,
    PMCR_INTERRUPT_COUNTER_MODE = 22,
    PMCR_NMI_COUNTER_MODE = 23,
    PMCR_TRAPA_INSTRUCTION_COUNTER_MODE = 24,
    PMCR_UBC_A_MATCH_MODE = 25,
    PMCR_UBC_B_MATCH_MODE = 26,
    PMCR_INSTRUCTION_CACHE_FILL_MODE = 33,
    PMCR_OPERAND_CACHE_FILL_MODE = 34,
    PMCR_ELAPSED_TIME_MODE = 35,
    PMCR_PIPELINE_FREEZE_BY_ICACHE_MISS_MODE = 36,
    PMCR_PIPELINE_FREEZE_BY_DCACHE_MISS_MODE = 37,
    PMCR_PIPELINE_FREEZE_BY_BRANCH_MODE = 39,
    PMCR_PIPELINE_FREEZE_BY_CPU_REGISTER_MODE = 40,
    PMCR_PIPELINE_FREEZE_BY_FPU_MODE = 41,
}

Variants

PMCR_INIT_NO_MODE = 0

PMCR_OPERAND_READ_ACCESS_MODE = 1

PMCR_OPERAND_WRITE_ACCESS_MODE = 2

PMCR_UTLB_MISS_MODE = 3

PMCR_OPERAND_CACHE_READ_MISS_MODE = 4

PMCR_OPERAND_CACHE_WRITE_MISS_MODE = 5

PMCR_INSTRUCTION_FETCH_MODE = 6

PMCR_INSTRUCTION_TLB_MISS_MODE = 7

PMCR_INSTRUCTION_CACHE_MISS_MODE = 8

PMCR_ALL_OPERAND_ACCESS_MODE = 9

PMCR_ALL_INSTRUCTION_FETCH_MODE = 10

PMCR_ON_CHIP_RAM_OPERAND_ACCESS_MODE = 11

PMCR_ON_CHIP_IO_ACCESS_MODE = 13

PMCR_OPERAND_ACCESS_MODE = 14

PMCR_OPERAND_CACHE_MISS_MODE = 15

PMCR_BRANCH_ISSUED_MODE = 16

PMCR_BRANCH_TAKEN_MODE = 17

PMCR_SUBROUTINE_ISSUED_MODE = 18

PMCR_INSTRUCTION_ISSUED_MODE = 19

PMCR_PARALLEL_INSTRUCTION_ISSUED_MODE = 20

PMCR_FPU_INSTRUCTION_ISSUED_MODE = 21

PMCR_INTERRUPT_COUNTER_MODE = 22

PMCR_NMI_COUNTER_MODE = 23

PMCR_TRAPA_INSTRUCTION_COUNTER_MODE = 24

PMCR_UBC_A_MATCH_MODE = 25

PMCR_UBC_B_MATCH_MODE = 26

PMCR_INSTRUCTION_CACHE_FILL_MODE = 33

PMCR_OPERAND_CACHE_FILL_MODE = 34

PMCR_ELAPSED_TIME_MODE = 35

PMCR_PIPELINE_FREEZE_BY_ICACHE_MISS_MODE = 36

PMCR_PIPELINE_FREEZE_BY_DCACHE_MISS_MODE = 37

PMCR_PIPELINE_FREEZE_BY_BRANCH_MODE = 39

PMCR_PIPELINE_FREEZE_BY_CPU_REGISTER_MODE = 40

PMCR_PIPELINE_FREEZE_BY_FPU_MODE = 41